Programmable logic resource technology is well known for its ability to allow a common hardware design (embodied in an integrated circuit) to be programmed to meet the needs of many different applications. To facilitate the use of programmable logic resources in certain applications, component blocks are coupled to programmable logic resource core circuitry. In one application, a component block is a block of logic or data that supports a communication or signaling protocol. These signaling protocols vary with respect to such parameters as clock signal frequency, header configuration, packet size, data word length, number of parallel channels, etc. Such signaling protocols can include, for example, industry-standard forms such as 10GBASE-R Ethernet, Interlaken, SFI-S, CPRI, etc., and any of a wide range of non-industry-standard or “custom” forms that particular users devise for their own uses. Custom protocols often have at least some features similar to industry-standard protocols, but deviate from industry standards in other respects.
There is increasing interest in using signaling protocols for high-speed communication between various devices in systems. For example, the devices in a system may be various integrated circuits that are mounted on a printed circuit board (“PCB”). The high-speed communication between the devices in such a system may take place via circuit traces on the PCB. One or more of the devices may be a PLD or that general type of relatively general-purpose, programmable or configurable device. All such devices to which the invention can be applied may sometimes be referred to generically as PLDs. This terminology is employed solely for convenience and is not intended to limit the invention to any particular narrow class of devices.
High-speed data communication may be supported on a PLD by including on the PLD some circuitry that is dedicated to performing certain tasks associated with such communication. Such dedicated circuitry may be referred to as a specialized block. The specialized block circuitry may be controllable, programmable, or configurable in some respects to adapt or customize it to particular communication protocols. Specialized blocks (rather than the general-purpose logic of the PLD) may be used for some aspects of high-speed communication for any of several reasons. These may include the need to provide higher-speed circuitry to keep up with the extremely fast bit rates of the communication, the large number of general-purpose logic elements that would be required to perform some of the complex encoding/decoding tasks required for some high-speed communication protocols, etc.
An important component in the circuitry required for many communication systems is a first-in-first-out (“FIFO”) circuit. FIFO circuits are used to buffer data between different systems, which may operate at the same or different clock frequencies. A FIFO typically includes read and write address pointers, a RAM to store data, and logic to generate status signals. Existing PLDs often contain a single FIFO block which is “hard-wired” for a particular protocol or function that imposes specific interface and clocking constraints on the user side. If multiple different protocols are desired, the PLD may repeat the single-FIFO architecture and include multiple different FIFO blocks, each specifically dedicated to a single protocol or use. Such a PLD would require separate user logic to interface with each of these blocks, which can be both redundant and cumbersome for the user. Additionally, such an architecture has a large footprint within the PLD.